FRDIV=000, IRCLKEN=0, IREFSTEN=0, CLKS=00, IREFS=0
MCG Control 1 Register
| IREFSTEN | Internal Reference Stop Enable 0 (0): Internal reference clock is disabled in Stop mode. 1 (1): Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. |
| IRCLKEN | Internal Reference Clock Enable 0 (0): MCGIRCLK inactive. 1 (1): MCGIRCLK active. |
| IREFS | Internal Reference Select 0 (0): External reference clock is selected. 1 (1): The slow internal reference clock is selected. |
| FRDIV | FLL External Reference Divider 0 (000): If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 1 (001): If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 2 (010): If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 3 (011): If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 4 (100): If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 5 (101): If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 6 (110): If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 7 (111): If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . |
| CLKS | Clock Source Select 0 (00): Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). 1 (01): Encoding 1 - Internal reference clock is selected. 2 (10): Encoding 2 - External reference clock is selected. 3 (11): Encoding 3 - Reserved. |